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This post illustrates the circuit design of Even Parity Generator. State Machine diagram for the same Parity Generator has been shown below. Click here to realize how we reach to the following state transition diagram.
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This chapter explains the VHDL programming for Combinational Circuits. VHDL Code for a Half-AdderVHDL Code:Library ieee;use ieee.stdlogic1164.all;entity halfadder isport(a,b:in bit; sum,carry:out bit);end halfadder;architecture data of halfadder isbeginsum.
Tutorial 2: AND Gates, OR Gates and Signals in VHDLCreated on: 7 December 2012In this second tutorial of the VHDL course, we look at two basic logic gates, namely the AND gate and the OR gate. We also look at signals in VHDL.An interesting problem can occur in a logic design that turns an AND gate into an OR gate. This same problem also turns an OR gate into an AND gate. These problems occur because of the external wiring of the logic system when it inverts inputs and outputs. VHDL signals are used to compensate for this problem in the CPLD circuit used in this tutorial.
In the VHDL code in this tutorial, you will see the name andor which is the name of the Xilinx project used with this tutorial. A single project was created to demonstrate both the AND and OR gates. This code is separated out in the first listings below to help explain each gate separately. AND Gates in VHDLThe VHDL for a two input AND gate is shown below:library IEEE;use IEEE.STDLOGIC1164.ALL;entity andortop isPort ( INA1: in STDLOGIC; - AND gate inputINA2: in STDLOGIC; - AND gate inputOA: out STDLOGIC; - AND gate outputend andortop;architecture Behavioral of andortop isbeginOA. Can't see the video?Creating the Project with the Xilinx ToolsThe project can be created using the above code and then using Xilinx PACE to create the UCF file to connect the inputs of the gates to switches on the switch bank and outputs to the LEDs.The pins used on the home made CPLD board for this tutorial are shown below in Xilinx PACE.Pin Assignment in Xilinx PACEThis connects the outer two switches of the switch bank to one gate and the outer two switches on the opposite side of the switch bank to the other gate. Source CodeThe project created for this tutorial is called andor and the VHDL file is called andortop.vhd.VHDL file, UCF file and JED file: (5.9kB)Entire Xilinx project: (690.6kB) Multiple Input AND and OR GatesA gate with any number of inputs can be created by stringing more inputs together with AND or OR statements. The following code shows a three input AND gate:X.
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